CV

Education

Ph.D. Electrical and Communication Engineering, Indian Institute of Science, Bangalore, 2015
M.Tech. Department of Electronic Systems Engineering (formerly CEDT), Indian Institute of Science, Bangalore, 2007
B.E. Electronics and Communication Engineering, M S Ramaiah Institute of Technology, Bangalore, India, 2005

2021-present: National University of Singapore (NUS), Research Fellow
- DDPM for AI: Implementation and testing of Dyadic Digital Pulse Modulation based high efficiency computing for ML applications in 40nm CMOS
- Side-Channel attack detection: Concept to silicon of side-channel attack detection using spectral analysis in 28nm CMOS
- Reconfigurable Cortex® multi-core: Technology setup, concept, std. cell design and characterization and implementation of ARM Cortex® based multi-core SoC in 22nm FD-SOI
2019–2021: Berkeley Education Alliance for Research in Singapore (BEARS), Postdoctoral Scholar
- In-Memory-Compute: Concept to silicon of in-memory-compute using new 9T SRAM cell for inference at the edge in video monitoring applications in 28nm CMOS
- E-skin:Concept to silicon of electronic skin interface decoder in 40nm CMOS
- In-Memory-Security: Combining physically unclonable function (PUF) and true random number generation (TRNG) in 8T-SRAM array in 28nm CMOS
2016–2019: National University of Singapore (NUS), Research Fellow
- EQNoC: Concept to fabrication and characterization of energy-quality scalable on-chip links to minimize energy for a given application in 28nm CMOS
- Machine Learning using EQNoC: Implementing ML algorithms using an energy quality scalable network-on-chip fabricated in 28nm CMOS

2007 - 2010: Analog Device Inc., Design Engineer
- Silicon debug and support, System level SPICE, RTL design and verification
Summer 2007: Philips, Intern
- Worked with the Philips television group (consumer electronics) on development of low cost EJTAG debugger – used in firmware development for televisions